Enlarging Spacer Thickness by Forming a Dielectric Layer Over a Recessed Interlayer Dielectric

ABSTRACT

An exemplary semiconductor device includes first spacers disposed along sidewalls of a first gate structure and second spacers disposed along sidewalls of a second gate structure. A source/drain region is disposed between the first gate structure and the second gate structure. A first ILD layer is disposed between the first spacers and the second spacers. A portion of the first ILD layer has a first recessed upper surface. A dielectric layer is disposed over the first spacers, the second spacers, and the first recessed upper surface of the first ILD layer. A portion of the dielectric layer has a second recessed upper surface that is disposed over the portion of the first ILD layer having the first recessed upper surface. A second ILD layer is disposed over the dielectric layer. A contact extends through the second ILD layer, the dielectric layer, and the first ILD layer to the source/drain region.

This is a divisional application of U.S. patent application Ser. No.16/891,992, filed Jun. 3, 2020, which is a continuation application ofU.S. patent application Ser. No. 16/166,762, filed Oct. 22, 2018, nowU.S. Pat. No. 10,679,989, which is a divisional application of U.S.patent application Ser. No. 15/063,907, filed Mar. 8, 2016, now U.S.Pat. No. 10,109,627, the entire disclosures of which are incorporatedherein by reference.

BACKGROUND

The semiconductor integrated circuit (IC) industry has experienced rapidgrowth. Technological advances in IC materials and design have producedgenerations of ICs where each generation has smaller and more complexcircuits than the previous generation. However, these advances haveincreased the complexity of processing and manufacturing ICs and, forthese advances to be realized, similar developments in IC processing andmanufacturing are needed. In the course of integrated circuit evolution,functional density (i.e., the number of interconnected devices per chiparea) has generally increased while geometry size (i.e., the smallestcomponent (or line) that can be created using a fabrication process) hasdecreased.

The ever-shrinking geometry size brings challenges to semiconductorfabrication. For example, misalignment between microelectroniccomponents (such as misalignment between a source/drain and a conductivecontact formed thereover) during fabrication may occur, which may damagethe semiconductor device or degrade its performance. In addition, thesmaller device sizes may lead to more significant parasitic capacitance,which could also negatively affect semiconductor device performance.

Therefore, while existing semiconductor devices and the fabricationthereof have been generally adequate for their intended purposes, theyhave not been entirely satisfactory in every aspect.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure is best understood from the following detaileddescription when read with the accompanying figures. It is emphasizedthat, in accordance with the standard practice in the industry, variousfeatures are not drawn to scale and are used for illustration purposesonly. In fact, the dimensions of the various features may be arbitrarilyincreased or reduced for clarity of discussion.

FIG. 1 is a perspective view of an example semiconductor device.

FIGS. 2-8 are different cross-sectional side views of a semiconductordevice according to various embodiments of the present disclosure.

FIG. 9 is a flowchart a method of fabricating a semiconductor device inaccordance with embodiments of the present disclosure.

DETAILED DESCRIPTION

It is understood that the following disclosure provides many differentembodiments, or examples, for implementing different features of theinvention. Specific examples of components and arrangements aredescribed below to simplify the present disclosure. These are, ofcourse, merely examples and are not intended to be limiting. Forexample, the formation of a first feature over or on a second feature inthe description that follows may include embodiments in which the firstand second features are formed in direct contact, and may also includeembodiments in which additional features may be formed between the firstand second features, such that the first and second features may not bein direct contact. In addition, the present disclosure may repeatreference numerals and/or letters in the various examples. Thisrepetition is for the sake of simplicity and clarity and does not initself dictate a relationship between the various embodiments and/orconfigurations discussed. Moreover, various features may be arbitrarilydrawn in different scales for the sake of simplicity and clarity.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. For example, if the device in the figures is turned over,elements described as being “below” or “beneath” other elements orfeatures would then be oriented “above” the other elements or features.Thus, the exemplary term “below” can encompass both an orientation ofabove and below. The apparatus may be otherwise oriented (rotated 90degrees or at other orientations) and the spatially relative descriptorsused herein may likewise be interpreted accordingly.

The present disclosure is directed to, but not otherwise limited to, afin-like field-effect transistor (FinFET) device. The use of FinFETdevices has been gaining popularity in the semiconductor industry. AFinFET device, for example, may be a complementarymetal-oxide-semiconductor (CMOS) device including a P-typemetal-oxide-semiconductor (PMOS) FinFET device and an N-typemetal-oxide-semiconductor (NMOS) FinFET device. In a typical FinFETdevice, a gate wraps around a fin structure, in which the source anddrain are formed. However, due at least in part to the narrowness of thefin structure, it may be challenging to align the source/drain with aconductive source/drain contact hole to be formed thereabove. A lateralshift of the source/drain contact hole (i.e., misalignment) mayinadvertently damage the gate, as the etching process used to form thesource/drain contact hole may cause the gate to be undesirably etched aswell.

To improve the alignment between the source/drain contact with thesource/drain, the present disclosure forms a recessed dielectric layerthat effectively serves as an “extra gate spacer”. This “extra gatespacer” protects the gate from being inadvertently etched. The variousaspects of the present disclosure are discussed below with reference toFIGS. 1-9. It is understood that the following disclosure will continuewith one or more FinFET examples to illustrate various embodiments ofthe present invention. It is understood, however, that the applicationshould not be limited to a particular type of device, except asspecifically claimed.

Referring to FIG. 1, a perspective view of an example FinFET device 50is illustrated. The FinFET device 50 is a non-planar multi-gatetransistor that is built on a substrate. A thin silicon “fin-like”structure (referred to as fin) forms the body of the FinFET device 50. Agate 60 of the FinFET device 50 is wrapped around this fin. Lg denotes alength (or width, depending on the perspective) of the gate 60. A source70 and a drain 80 of the FinFET device 50 are formed in extensions ofthe fin on opposite sides of the gate 60. The fin itself serves as achannel. The effective channel length of the FinFET device 50 isdetermined by the dimensions of the fin.

FinFET devices offer several advantages over traditional Metal-OxideSemiconductor Field Effect Transistor (MOSFET) devices (also referred toas planar devices). These advantages may include better chip areaefficiency, improved carrier mobility, and fabrication processing thatis compatible with the fabrication processing of planar devices. Thus,it may be desirable to design an integrated circuit (IC) chip usingFinFET devices for a portion of, or the entire IC chip.

Referring now to FIG. 2, a semiconductor device 100 is illustrated. Thesemiconductor device 100 shown in FIG. 2 is a diagrammaticcross-sectional side view of a FinFET device taken along the X-Z planeof FIG. 1. The semiconductor device 100 includes a substrate 110. In anembodiment, the substrate 110 includes a dielectric material, forexample silicon oxide (SiO₂). In other embodiments, the substrate 110may include another suitable material, for example a semiconductormaterial.

A semiconductor layer 130 is formed on the substrate 110. In anembodiment, the semiconductor layer 130 includes a crystal siliconmaterial. It is understood that the semiconductor layer 130 may includeother suitable materials in alternative embodiments. An implantationprocess may be performed to implant a plurality of dopant ions to thesemiconductor layer 130. The dopant ions may include an n-type materialin some embodiments, for example arsenic (As) or phosphorous (P), orthey may include a p-type material in some other embodiments, forexample boron (B), depending on whether an NMOS or a PMOS is needed.After the implantation process is performed, a doping concentrationlevel in the semiconductor layer 130 is in a range from about 1×10¹⁷ions/cm³ to about 5×10¹⁹ ions/cm³ in some embodiments. In otherembodiments, the doping concentration levels and the thickness of thesubstrate may be different.

The semiconductor layer 130 is patterned to form a fin structure (e.g.,the fin structure shown in FIG. 1). The fin structure extends in anelongate manner along the X direction. As discussed previously, aportion of the fin structure will serve as a conductive channel for thesemiconductor device 100, and another portion of the fin structure willserve as the source/drain region of the semiconductor device 100.

The semiconductor device 100 includes gate structures 140. The gatestructures 140 are formed to wrap around the fin structure in the manneras shown in FIG. 1. However, since FIG. 2 illustrates thecross-sectional side view of the FinFET device taken across the X-Zplane (i.e., cutting the FinFET device on the fin structure), only aportion of each of the gate structures 140 is shown. That is, FIG. 2shows the portion of the gate structures 140 disposed over the finstructure, but not the portion of the gate structures 140 disposedbeside the fin structure.

Each gate structure 140 includes a respective gate dielectric layer thatis formed around the fin structure and a gate electrode layer that isformed on the gate dielectric layer. The gate dielectric layer and thegate electrode layer may each be formed using a deposition process knownin the art, for example chemical vapor deposition (CVD), physical vapordeposition (PVD), atomic layer deposition (ALD), combinations thereof,or another suitable process.

In some embodiments, the gate structures 140 are high-k metal gatestructures. In these embodiments, the gate dielectric layer contains ahigh-k dielectric material. A high-k dielectric material is a materialhaving a dielectric constant that is greater than a dielectric constantof SiO₂, which is approximately 4. In an embodiment, the gate dielectriclayer contains hafnium oxide (HfO₂), which has a dielectric constantthat is in a range from approximately 18 to approximately 40. Inalternative embodiments, the gate dielectric layer may contain one ofZrO₂, Y₂O₃, La₂O₅, Gd₂O₅, TiO₂, Ta₂O₅, HfErO, HfLaO, HfYO, HfGdO, HfAlO,HfZrO, HfTiO, HfTaO, and SrTiO. The gate electrode layer contains ametal or metal compound. For example, the gate electrode layer maycontain titanium nitride (TiN) material, tungsten (W), tungsten nitride(WN), or tungsten aluminum (WAl), aluminum (Al), titanium (Ti), copper(Cu), or combinations thereof.

The formation of the high-k metal gate may involve a gate replacementprocess flow. In one embodiment of the gate replacement process flow, adummy gate electrode layer (e.g., containing polysilicon) is formed on ahigh-k gate dielectric layer. After ion implantation processes areperformed to form the source and drain regions (discussed below in moredetail), the dummy gate electrode layer is removed, and then a metalgate electrode layer is formed in place of the dummy gate electrodelayer. This gate replacement process flow may be referred to as agate-last process flow. In another embodiment of the gate replacementprocess flow, a dummy gate dielectric layer (e.g., containing siliconoxide) is formed, and the dummy gate electrode layer is formed over thedummy gate dielectric layer. After ion implantation processes areperformed to form the source and drain regions, the dummy gatedielectric layer and the dummy gate electrode layer are both removed. Ahigh-k gate dielectric layer is formed to replace the dummy gatedielectric layer, and a metal gate electrode layer is formed to replacethe dummy gate electrode layer. This gate replacement process flow maybe referred to as a high-k-last process flow. As an example, the detailsof forming high-k metal gate structures are described in more detail inU.S. patent application Ser. No. 13/440,848, filed on Apr. 5, 2012,entitled “Cost-effective gate replacement process” to Zhu et al., whichis issued as U.S. Pat. No. 8,753,931 on Jun. 17, 2014, the disclosure ofwhich is hereby incorporated by reference in its entirety.

Gate spacers 150 are formed on sidewall surfaces of the gate structures140. The gate spacers 150 are formed by depositing a spacer materialover the gate structures 140 and thereafter performing a patterningprocess (for example an etching process) on the spacer material. Thespacer material may include a dielectric material. In an embodiment, thespacer material includes silicon oxide. In another embodiment, thespacer material includes silicon nitride.

Still referring to FIG. 2, a channel region is disposed below each ofthe gate structures 140 in a portion of the semiconductor layer 130. Asource/drain region 160 is formed in another portion of thesemiconductor layer 130, between the gate structures 140. Alternativelystated, source/drain regions 160 (one of which is shown in FIG. 2) areformed on opposite sides of each of the gate structures 140. In someembodiments, the source/drain region 160 may include a lightly dopedsource/drain region and a heavily doped source/drain region. The lightlydoped source/drain region may be formed by an ion implantation processin which dopant ions are implanted into the portion of the fin structurelocated on either side (or opposite sides) of the gate structures 140.The ion implantation process used to form the lightly doped source/drainregion is performed before the gate spacers 150 are formed. After theformation of the gate spacers, another ion implantation process isperformed to implant dopant ions into the portion of the fin structurenot protected by the gate structures 140 or the gate spacers 150. Thision implantation process forms the heavily doped source/drain regions,which have a greater dopant concentration level than the lightly-dopedsource/drain regions.

The semiconductor device 100 also includes an interlayer dielectric(ILD) 180. In the embodiment illustrated in FIG. 2, the ILD 180 isdisposed laterally adjacent to the gate spacers 150 and vertically abovethe source/drain region 160. In some embodiments, the ILD 180 contains alow-k dielectric material (dielectric constant smaller than that ofsilicon oxide). For example, the low-k dielectric material may includefluorine-doped silicon dioxide, carbon-doped silicon dioxide, poroussilicon dioxide, porous carbon-doped silicon dioxide, or a spin-onpolymeric dielectric material. As is shown in FIG. 2, the ILD 180 has aplanar (or flat) upper surface 200 that is co-planar with the uppersurface of the gate structures 140.

Referring now to FIG. 3, a process 210 is performed to the semiconductordevice 100 to form a recess 220 in the upper surface 200 of the ILD. Insome embodiments, the process 210 includes one or more etchingprocesses. The etching processes may include a wet etching process, adry etching process, or a combination thereof. The one or more etchingprocesses are configured to etch away the material of the ILD 180without substantially etching away the materials of the gate structures140 or the gate spacers 150. For example, this may be done byconfiguring the etchant to have a substantially higher etching rate withrespect to the material of the ILD 180 than with respect to thematerials of the gate structures 140 or the gate spacers 150.

In some other embodiments, the process 210 includes one or morepolishing processes such as a chemical mechanical polishing (CMP)process. The CMP process uses a carefully-tuned slurry that is differentfrom the slurries in conventional CMP processes, so that the material ofthe ILD 180 is polished away at a faster rate than the materials of thegate structures 140 or the materials of the gate spacers 150.

Regardless of how the process 210 is implemented, the result is that thepartial removal of the ILD 180 causes an opening 220 to be formed overthe ILD 180. Or stated differently, the ILD 180 is “caved in” and has arecessed upper surface 200A. The recessed upper surface 200A slopesdownward (toward the substrate 110). The recessed upper surface 200A mayalso have a downward curvature in some embodiments. In some embodiments,the removal of the ILD 180 causes an upper portion of the gate spacers150 to be exposed to be opening 220. In other words, the gate spacers150 (that are disposed next to the ILD 180) each have a portion 230 of asidewall surface that is exposed.

It is understood that according to conventional semiconductorfabrication, the process 210 would not have been performed. The process210 is performed according to the various aspects of the presentdisclosure in order to allow a subsequently formed dielectric layer toeffectively enlarge the thickness of the gate spacers 150, as discussedbelow in more detail.

Referring now to FIG. 4, a dielectric layer 250 is formed over the gatestructures 140 and over the ILD 180. The dielectric layer 250 at leastpartially fills the opening 220 and is in direct physical contact withthe ILD 180 and the portions 230 of the upper sidewall surfaces of thegate spacers 150. In some embodiment, the dielectric layer 250 is formedby a conformal deposition process, and as a result, an upper surface 260of the dielectric layer 250 partially assumes the recessed shape orprofile of the recessed upper surface 200A of the ILD 180. In otherwords, the dielectric layer 250 is also formed to have a recessed uppersurface 260. This allows portions of the dielectric layer 250 to belaterally disposed on the portions 230 of the sidewalls of the gatespacers 150. In some embodiments, the dielectric layer 250 is anetching-stop layer (ESL) and has a different material composition thanthe ILD 180. The dielectric layer 250 may or may not have the samematerial composition as the gate spacers 150. In some embodiments, thedielectric layer 250 contains silicon nitride.

Referring now to FIG. 5, another dielectric layer 280 is formed over thedielectric layer 250. The dielectric layer 280 may be formed by asuitable deposition process. The dielectric layer 280 is also consideredan interlayer dielectric (ILD) and may be referred to as ILD 280hereinafter. In some embodiments, the ILD 280 and the ILD 180 have thesame material compositions, for example they may both contain a low-kdielectric material. However, the ILD 280 and the dielectric layer 250have different material compositions.

Referring now to FIG. 6, a contact hole 300 is formed using variousetching processes. The contact hole 300 extends vertically through theILD 280, the dielectric layer 250, and the ILD 180. The contact hole 300exposes a portion of the source/drain region 160. During the etching ofthe contact hole 300, a portion 250A of the dielectric layer 250effectively serves as an extra gate spacer to protect the gatestructures 140 from being damaged. In more detail, since the dielectriclayer 250 is formed on the recessed upper surface 200A (see FIG. 4) ofthe ILD 180, the dielectric layer 250 assumes the recessed shape/profileof the upper surface 200A of the ILD 180, and a portion 250A of thedielectric layer 250 disposed directly on the portion 230 of thesidewall of each of the gate spacers 150. The portion 250A of thedielectric layer 250 effectively “thickens” the gate spacers 150.Alternatively stated, the gate spacers 150 may be viewed as having anincreased lateral thickness at the top portions.

During the etching of the contact hole 300, a lateral shift may occur.In more detail, the contact hole 300 may shift laterally toward eitherof the gate structures 140. This is undesirable, because as the contacthole 300 shifts too close to either of the gate structure 140 s, thegate spacer 150 of that gate structure 140 may be “punched through.” Inother word, enough of the gate spacers 150 may be etched away (due tothe lateral shift of the contact hole 300), so that they can no longerprotect the gate structure 140 from being etched. As a result, the gatestructure 140 may be damaged by the etching performed to form thecontact hole 300. However, since the portions 250A of the dielectriclayer 250 effectively “thickens” the gate spacers 150, the“punch-through” of the gate spacers 150 is more difficult. Stateddifferently, even if the contact hole 300 is undesirably shiftedlaterally toward either of the gate structures 140, the effectively“thicker” gate spacer 150 can more adequately prevent itself from being“punched through”, and thus the gate spacers 150 can better protect thegate structures 140 from being inadvertently damaged during theformation of the contact hole 300.

Note that this would not have been possible if the ILD 180 had not beenformed to have a recessed upper surface. Had the ILD 180 been left alonewith a planar/flat upper surface 200 as shown in FIG. 2, the subsequentformation of the dielectric layer 250 thereon would have been over (orabove) the gate spacers 150. In other words, no portion of thedielectric layer 250 would have been formed on the sidewalls of the gatespacers 150, and as such, the gate spacers 150 would not have had theincreased lateral thickness as they do according to the presentdisclosure.

Referring now to FIG. 7, a source/drain contact 350 is formed in thecontact hole 300. The source/drain contact 350 may be formed by fillingthe contact hole 300 with a conductive material, for example via adeposition process, and then polishing away the excess portions of theconductive material outside the contact hole 300. The remaining portionof the conductive material forms the source/drain contact 350. In someembodiments, the source/drain contact 350 contains tungsten. In otherembodiments, the source/drain contact 350 contains aluminum or copper.The source/drain contact 350 is electrically coupled to the source/drain160 (e.g., through physical contact) and provides electricalconnectivity to the source/drain 160.

Since the source/drain contact 350 and the gate electrode of thestructure 140 are both conductive, and since the materials disposedtherebetween (e.g., the ILD 180 and the gate spacers 150) aredielectric, this leads to parasitic capacitance, as capacitance ariseswhen a dielectric material is disposed between two conductive plates.Capacitance is inversely correlated to a distance between the twoconductive plates. In other words, as the distance increases between thetwo conductive plates, capacitance decreases; as the distance decreasesbetween the two conductive plates, capacitance increases. In aconventionally fabricated semiconductor device, the lateral shift of thesource/drain contact hole decreases the distance between the twoconductive plates (i.e., the source/drain contact 350 and the gatestructure 140). The gate spacer 150 may help prevent the source/draincontact hole from being etched too close to the gate structure 140, butsince the gate spacer 150 is thin (especially at the top), this may notbe sufficient. Consequently, parasitic capacitance arising from thesource/drain contact 350 being formed too close (i.e., small distance)to the gate structure 140 may become significant, especially assemiconductor device sizes get smaller with each technology generation.This parasitic capacitance adversely affects semiconductor deviceperformance.

In comparison, the present disclosure reduces the parasitic capacitanceby effectively “enlarging” the spacers 150 with the portions 250A of thedielectric layer 250 disposed on the sidewalls 230 of the spacers 150.Due to the “enlarged” or “thicker” spacers 150, it is more difficult forthe source/drain contact hole to punch it through. In other words, thesource/drain contact hole is formed in a more self-aligned manner (i.e.,better vertically aligned with the source/drain region 160). Thus, theeffective distance between the source/drain contact 350 and the gateelectrode of the gate structure 140 is increased, compared to a scenarioin prior fabrication where lateral shift of the source/drain contactmade such distance too small.

It is understood that the amount or degree of recess formed in the ILD180 may be dependent on the type of semiconductor device 100. Forexample, the semiconductor device 100 may be an Input/Output (I/O)device. I/O devices include devices that handle the input and/or outputvoltages/currents, and as such they need to be able to tolerate agreater amount of voltage or current swing than non-I/O devices. Incomparison, non-I/O devices may include core devices, which may includelogic devices (that do not need to handle the input/outputvoltages/currents directly). For example, the core devices may includevarious logic gates such as NAND, NOR, INVERTER, etc. In someembodiments, the core devices include an SRAM (static random-accessmemory) region.

One physical difference between the I/O device and the non-I/O device isthat the distance between adjacent gate structures is longer for an I/Odevice than for a non-I/O device. In other words, the ILD 180 for an I/Odevice is wider than the ILD for a non-I/O device. For example, FIG. 8illustrates a semiconductor device 400 that is a non-I/O device (e.g., acore device) but is otherwise similar to the I/O device 100 of FIG. 7.The non-I/O device 400 undergoes substantially similar fabricationprocesses discussed above with reference to FIGS. 2-7 to form the I/Odevice 100. Therefore, for reasons of clarity and consistency, similarcomponents will be labeled the same for the non-I/O device 400 of FIG. 8and for the I/O device 100 of FIG. 7.

In addition to the differences in ILD widths, another difference betweenthe non-I/O device 400 in FIG. 8 and the I/O device 100 in FIG. 7 isthat the non-I/O device 400 has a less recessed ILD 180 (and thus a lessrecessed dielectric layer 250) than the I/O device 100. In someembodiments, the less recessed ILD 180 means that the upper surface ofthe ILD 180 (or the upper surface 260 of the dielectric layer 250) ofthe non-I/O device 400 is shallower than the upper surface of the ILD180 (or the upper surface 260 of the dielectric layer 250) of the I/Odevice 100. For example, the difference between the ILD depths for theI/O device 100 and the non-I/O device 400 is at least 1 nm. In otherembodiments, the less recessed ILD 180 also means that the upper surfaceof the ILD 180 of the non-I/O device 400 is less curved than the uppersurface of the ILD 180 of the I/O device 100. The same may be said aboutthe upper surface 260 of the dielectric layer 250 for the I/O device 100and the non-I/O device 400.

One reason for the more recessed ILD 180 for the I/O device 100 is thatI/O devices need to handle greater amounts of voltage/current, andparasitic capacitance may be a greater concern in that situation. Thus,the more recessed ILD 180 for the I/O device 100 can better alleviatethe concerns of parasitic capacitance by making sure that enoughdielectric material will be formed on the upper sidewalls of the spacers(due to the more recessed ILD), which effectively thickens the spacer150 as discussed above.

It is understood that additional fabrication processes may be performedto complete the fabrication of the semiconductor device 100. Forexample, gate contacts may be formed, and a multi-layered interconnectstructure containing a plurality of metal lines and vias may also beformed. The semiconductor device 100 may also undergo packaging andtesting processes. For reasons of simplicity, these additional processesare not discussed in detail herein. In addition, though the processesdiscussed above with reference to FIGS. 1-8 are performed using a FinFETas an example semiconductor device, it is understood that the variousaspects of the present disclosure (and their benefits) also apply to“planar” non-FinFET devices as well.

FIG. 9 is a flowchart of a method 600 for fabricating a semiconductordevice in accordance with embodiments of the present disclosure. Themethod 600 includes a step 610 of receiving a device that includes asource/drain, a gate, a gate spacer formed on a sidewall of the gate,and a dielectric component formed over the source/drain. The gate spaceris formed between the gate and the dielectric component. In someembodiments, the receiving of the device comprises receiving a FinFET asthe device. The FinFET device includes a fin structure in which thesource/drain is formed, and the gate is formed to wrap around the finstructure.

The method 600 includes a step 620 of forming a recess in a top surfaceof dielectric component. In some embodiments, the forming of the recesscomprises performing a chemical-mechanical polishing (CMP) process tothe gate and the dielectric component. A slurry of the CMP process isconfigured such that the dielectric component is polished at a fasterrate than the gate. In some other embodiments, the forming of the recesscomprises removing portions of the dielectric component via an etchingprocess. The etching process may include a wet etching process or a dryetching process.

The method 600 includes a step 630 of forming a dielectric layer overthe top surface of the dielectric component and over the recess, suchthat a portion of the dielectric layer assumes a recessed shape.

The method 600 includes a step 640 of etching a contact hole through thedielectric layer and the dielectric component, the contact hole exposingthe source/drain.

The method 600 includes a step 650 of filling the contact hole with aconductive material, thereby forming a source/drain contact.

In some embodiments, the forming of the recess is performed such that aportion of a sidewall of the gate spacer is exposed, and the forming thedielectric layer is performed such that a portion of the dielectriclayer is formed directly on the exposed portion of the sidewall of thegate spacer. The portion of the dielectric layer remains on the sidewallof the gate spacer after the contact hole is etched.

In some embodiments, the receiving the device in step 610 comprisesreceiving a non-Input/Output (non-I/O) device and an Input/Output (I/O)device that each include their respective source/drain, gate, gatespacer, and dielectric component. The dielectric component of the I/Odevice is formed to have a greater lateral dimension than the dielectriccomponent of the non-I/O device. In some embodiments, the forming of therecess in step 620 is performed such that the I/O device is formed tohave a deeper recess than the non-I/O device.

It is understood that additional process steps may be performed before,during, or after the steps 610-650 discussed above to complete thefabrication of the semiconductor device. For example, the semiconductordevice may undergo testing and packaging processes before thefabrication is completed. Other process steps are not discussed hereinfor reasons of simplicity.

Based on the above discussions, it can be seen that the presentdisclosure offers advantages over conventional semiconductor devices andthe fabrication thereof. It is understood, however, that otherembodiments may offer additional advantages, and not all advantages arenecessarily disclosed herein, and that no particular advantage isrequired for all embodiments.

One advantage is that the semiconductor device of the present disclosurecan reduce potential damage caused by misalignment between thesource/drain and the source/drain contact hole. As discussed above,instead of leaving the ILD planarized, the present disclosure usesetching or carefully tuned polishing processes to make the ILD“caved-in” or recessed. The subsequent deposition of a dielectric layeron the recessed ILD effectively enlarges or thickens the spacers. As aresult, the etching processes used to form the source/drain contactholes cannot easily pierce through the “thickened” spacers, and thisprevents the gate structures from being damaged.

Along similar lines, another advantage is that the “thickened” spacerscan relax the overlay requirements or the etching process loadingassociated with the formation of the source/drain contact hole. This isbecause even if there is some lateral shift of the source/drain contacthole, the consequences are unlikely to be disastrous, as the “thickened”spacers formed herein can still adequately protect the gate structures.

Furthermore, the present disclosure also offers the advantage ofreducing parasitic capacitance. In the context of the presentdisclosure, parasitic capacitance is an inverse function of a distancebetween the gate structure and the source/drain contact. The “thickened”spacers herein ensure that the source/drain contact does not get “tooclose” to the gate structure on either side. In other words, the“thickened” spacers effectively lengthen a minimum distance between thegate structures and the source/drain contact. As this distanceincreases, the resulting parasitic capacitance is reduced. The reductionof parasitic capacitance improves yield and enhances semiconductordevice performance.

One aspect of the present disclosure involves a semiconductor device.The semiconductor device includes a transistor. The transistor includesa source/drain region, a gate structure, a gate spacer disposed on asidewall of the gate structure, a first dielectric material disposedadjacent to an upper portion of the gate spacer, and a second dielectricmaterial disposed adjacent to a lower portion of the gate spacer. Thesecond dielectric material and the first dielectric material havedifferent material compositions.

Another aspect of the present disclosure involves a semiconductordevice. The semiconductor device includes a non-Input/Output (non-I/O)device. The non-I/O device includes a first source/drain, a first gatestructure, a first gate spacer disposed on a sidewall of the first gatestructure, a first interlayer dielectric (ILD) disposed next to thefirst gate spacer, a first dielectric layer disposed over the first gatestructure and over the first ILD, the first dielectric layer having afirst recessed upper surface, and a first contact disposed over thefirst source/drain. The first contact extends through the first ILD andthe first dielectric layer. The semiconductor device also includes anInput/Output (I/O) device. The I/O device includes a secondsource/drain, a second gate structure, a second gate spacer disposed ona sidewall of the second gate structure, a second interlayer dielectric(ILD) disposed next to the second gate spacer, a second dielectric layerdisposed over the second gate structure and over the second ILD, thesecond dielectric layer having a second recessed upper surface, and asecond contact disposed over the second source/drain. The second contactextends through the second ILD and the second dielectric layer. Thesecond recessed upper surface has a greater depth than the firstrecessed upper surface.

Yet another aspect of the present disclosure involves a method offabricating a semiconductor device. A device is received that includes asource/drain, a gate, a gate spacer formed on a sidewall of the gate,and a dielectric component formed over the source/drain. The gate spaceris formed between the gate and the dielectric component. A recess isformed in a top surface of the dielectric component. A dielectric layeris formed over the top surface of the dielectric component and over therecess, such that a portion of the dielectric layer assumes a recessedshape. A contact hole is etched through the dielectric layer and thedielectric component. The contact hole exposes the source/drain.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

What is claimed is:
 1. A method comprising: forming a first dielectriclayer over a gate stack and gate spacers disposed along sidewalls of thegate stack, wherein the gate stack is disposed over and wraps a channelof a fin structure extending from a substrate, the gate stack includes agate dielectric and a gate electrode, and the gate stack is disposedbetween source/drain regions of the fin structure; recessing the firstdielectric layer to expose an upper portion of one of the gate spacers,wherein a remaining portion of the first dielectric layer is disposedadjacent to a lower portion of the one of the gate spacers; depositing asecond dielectric layer over the remaining portion of the firstdielectric layer, a top surface of the gate stack, and the gate spacers,wherein the second dielectric layer is disposed adjacent to the upperportion of the one of the gate spacers and a first composition of thefirst dielectric layer is different than a second composition of thesecond dielectric layer; forming a source/drain contact opening thatextends through the second dielectric layer and the first dielectriclayer to expose one of the source/drain regions of the fin structure;and forming a source/drain contact in the source/drain contact opening,wherein the first dielectric layer is disposed between the source/draincontact and the lower portion of the one of the gate spacers and thesecond dielectric layer is disposed between the source/drain contact andthe upper portion of the one of the gate spacers.
 2. The method of claim1, further comprising, depositing a third dielectric layer over thesecond dielectric layer before forming the source/drain contact opening,wherein the third dielectric layer further extends over the top surfaceof the gate stack, the second composition of the second dielectric layeris different than a third composition of the third dielectric layer, andthe source/drain contact opening extends through the third dielectriclayer.
 3. The method of claim 2, wherein the depositing the seconddielectric layer includes performing a conformal deposition process,such that the second dielectric layer has a curved top surface over thefirst dielectric layer and a flat top surface over the top surface ofthe gate stack, and wherein the second dielectric layer and the thirddielectric layer have a curvilinear interface therebetween and a linearinterface therebetween.
 4. The method of claim 1, wherein the recessingthe first dielectric layer to expose the upper portion of the one of thegate spacers includes performing a planarization process that uses aslurry tuned to polish the first composition of the first dielectriclayer at a faster rate than a third composition of the gate spacers anda fourth composition of the gate stack.
 5. The method of claim 1,wherein the recessing the first dielectric layer to expose the upperportion of the one of the gate spacers includes performing an etchingprocess that uses an etchant tuned to etch the first composition of thefirst dielectric layer at a faster rate than a third composition of thegate spacers and a fourth composition of the gate stack.
 6. The methodof claim 1, wherein the recessing the first dielectric layer providesthe first dielectric layer with a curved surface, such that the firstdielectric layer and the second dielectric layer have a curvilinearinterface therebetween.
 7. The method of claim 1, wherein the secondcomposition of the second dielectric layer is the same as a thirdcomposition of the gate spacers.
 8. The method of claim 1, wherein thesecond composition of the second dielectric layer is different than athird composition of the gate spacers.
 9. A method comprising: forming afirst FinFET having a first gate stack, first gate spacers disposedalong first sidewalls of the first gate stack, and a first finstructure, wherein the first gate stack is disposed over and wraps afirst channel of the first fin structure and is further disposed betweenfirst source/drain regions of the first fin structure; forming a secondFinFET having a second gate stack, second gate spacers disposed alongsecond sidewalls of the second gate stack, and a second fin structure,wherein the second gate stack is disposed over and wraps a secondchannel of the second fin structure and is further disposed betweensecond source/drain regions of the second fin structure; forming a firstdielectric layer over the first gate stack, the first gate spacersdisposed along the first sidewalls of the first gate stack, the secondgate stack, and the second gate spacers disposed along the secondsidewalls of the second gate stack; recessing the first dielectric layerto expose a first upper portion of one of the first gate spacers and asecond upper portion of one of the second gate spacers, wherein aremaining portion of the first dielectric layer is disposed adjacent toa first lower portion of the one of the first gate spacers and a secondlower portion of the one of the second gate spacers; depositing a seconddielectric layer over the remaining portion of the first dielectriclayer, a first top surface of the first gate stack, the first gatespacers, a second top surface of the second gate stack, and the secondgate spacers, wherein the second dielectric layer is disposed adjacentto the first upper portion of the one of the first gate spacers and thesecond upper portion of one of the second gate spacers, and furtherwherein a first composition of the first dielectric layer is differentthan a second composition of the second dielectric layer; forming afirst source/drain contact opening and a second source/drain contactopening that extends through the second dielectric layer and the firstdielectric layer to expose one of the first source/drain regions of thefirst fin structure and one of the second source/drain regions of thesecond fin structure, respectively; and forming a first source/draincontact in the first source/drain contact opening and a secondsource/drain contact in the second source/drain contact opening,wherein: the first dielectric layer is disposed between the firstsource/drain contact and the first lower portion of the one of the firstgate spacers, the first dielectric layer is disposed between the secondsource/drain contact and the second lower portion of the one of thesecond gate spacers, the first dielectric layer is disposed between thesecond dielectric layer and each of the first fin structure and thesecond fin structure, the second dielectric layer extends over the firsttop surface of the first gate stack and the second top surface of thesecond gate stack, the second dielectric layer is disposed between thefirst source/drain contact and the first upper portion of the one of thefirst gate spacers, and the second dielectric layer is disposed betweenthe second source/drain contact and the second upper portion of the oneof the second gate spacers.
 10. The method of claim 9, wherein: thefirst dielectric layer that is disposed between the first source/draincontact and the first lower portion of the one of the first gate spacershas a first width; the first dielectric layer that is disposed betweenthe second source/drain contact and the second lower portion of the oneof the second gate spacers has a second width; and the first width isdifferent than the second width.
 11. The method of claim 9, wherein therecessing of the first dielectric layer forms: a first recessed topsurface of the first dielectric layer that is disposed adjacent to thefirst lower portion of the one of the first gate spacers; a secondrecessed top surface the first dielectric layer that is disposedadjacent to the second lower portion of the one of the second gatespacers; and wherein a first distance between a first top fin surface ofthe first fin structure and the first recessed top surface is differentthan a second distance between a second top fin surface of the secondfin structure and the second recessed top surface.
 12. The method ofclaim 11, wherein a difference between the first distance and the seconddistance is at least one nanometer.
 13. The method of claim 9, whereinthe recessing the first dielectric layer includes selectively removingthe first dielectric layer without substantially removing the first gatespacers and the second gate spacers.
 14. The method of claim 13, whereinthe selectively removing includes using a slurry that polishes the firstdielectric layer at a first rate and the first gate spacers and thesecond gate spacers at a second rate that is lower than the first rate.15. The method of claim 13, wherein the selectively removing includesusing an etchant that etches the first dielectric layer at a first rateand the first gate spacers and the second gate spacers at a second ratethat is lower than the first rate.
 16. A method comprising: forming afin structure over a substrate; forming a first gate stack over andwrapping a first channel of the fin structure and a second gate stackover and wrapping a second channel of the fin structure, wherein thefirst gate stack includes a first gate dielectric and a first gateelectrode, the second gate stack includes a second gate dielectric and asecond gate electrode, and a source/drain region of the fin structure isdisposed between the first gate stack and the second gate stack; formingfirst gate spacers along first sidewalls of the first gate stack andsecond gate spacers along second sidewalls of the second gate stack;forming a first low-k silicon oxide layer over the source/drain regionof the fin structure, a silicon nitride layer over the first low-ksilicon oxide layer, and a second low-k silicon oxide layer over thesilicon nitride layer, wherein the silicon nitride layer extends over afirst top surface of the first gate stack and a second top surface ofthe second gate stack and the second low-k silicon oxide layer extendsover the first top surface of the first gate stack and the second topsurface of the second gate stack; and forming a source/drain contactthat extends through the second low-k silicon oxide layer, the siliconnitride layer, and the first low-k silicon oxide layer to thesource/drain region of the fin structure, wherein the first low-ksilicon oxide layer is disposed between the source/drain contact and afirst lower portion of the first gate spacers, the first low-k siliconoxide layer is disposed between the source/drain contact and a secondlower portion of the second gate spacers, the silicon nitride layer isdisposed between the source/drain contact and a first upper portion ofthe first gate spacers, and the silicon nitride layer is disposedbetween the source/drain contact and a second upper portion of thesecond gate spacers.
 17. The method of claim 16, wherein the forming thefirst low-k silicon oxide layer includes recessing the first low-ksilicon oxide layer before forming the silicon nitride layer, such thatan interface between the first low-k silicon oxide layer and the siliconnitride layer is curved.
 18. The method of claim 16, wherein therecessing the first low-k silicon oxide layer provides the first low-ksilicon oxide layer with a topmost surface that is below the first topsurface of the first gate stack and the second top surface of the secondgate stack.
 19. The method of claim 16, wherein a first width of thesilicon nitride layer that is disposed between the source/drain contactand the first upper portion of the first gate spacers is different thana second width of the silicon nitride layer that is disposed between thesource/drain contact and the second upper portion of the second gatespacers.
 20. The method of claim 16, wherein a first width of thesilicon nitride layer that is disposed between the source/drain contactand the first upper portion of the first gate spacers is the same as asecond width of the silicon nitride layer that is disposed between thesource/drain contact and the second upper portion of the second gatespacers.